Summary of STMICROELECTRONICS STM32H7A3/7B3 LINES OF MICROCONTROLLERS INCLUDE AN ARM® CORTEX®-M7 CORE
Summary: The STM32H7A3/7B3 microcontroller lines feature an Arm Cortex-M7 core (double-precision FPU) up to 280 MHz, 1–2 MB Flash, 1.414 MB SRAM with TCM (ITCM/DTCM), advanced security (crypto accel, on-the-fly Octo-SPI decryption, SFI, SBSFU), low-power modes with embedded SMPS, high performance via L1 caches, and enhanced graphics support (LCD-TFT, Chrom-ART, Chrom-GRC, JPEG accelerator). Available in 64–225 pin BGA and LQFP packages.
Parts used in the STM32H7A3/7B3 Microcontroller Project:
- Arm Cortex-M7 core with double-precision FPU
- 1 to 2 Mbytes Flash memory
- 1.414 Mbytes SRAM (192 KB TCM: 64 KB ITCM + 128 KB DTCM; 1.18 MB user SRAM; 4 KB backup SRAM)
- L1 cache (16 KB I-cache + 16 KB D-cache)
- Octo-SPI external serial flash memory (supported for on-the-fly decryption)
- Crypto/hash hardware acceleration block
- Secure Firmware Install (SFI) security services
- Secure Boot Secure Firmware Update (SBSFU)
- Dual-power domain architecture
- Embedded SMPS (switch-mode power supply)
- LDO (low-dropout regulator) for power management combination
- LCD-TFT controller interface with dual-layer support
- Chrom-ART Accelerator
- Chrom-GRC memory optimization
- JPEG hardware accelerator
- BGA and LQFP package options (64- to 225-pin)
The STM32H7A3/7B3 lines of microcontrollers include an Arm® Cortex®-M7 core (with double-precision floating point unit) running up to 280 MHz.
The STM32H7A3/7B3 MCU lines provides 1 to 2 Mbytes Flash memory, 1.4 Mbytes of SRAM with the following architecture: 192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes and 64- to 225-pin packages in BGA and LQFP profiles.
Performance
- 280 MHz fCPU/, 1414 CoreMark /599 DMIPS executing from Flash memory, with 0-wait states thanks to its L1 cache.
- L1 cache (16 Kbytes of I-cache +16 Kbytes of D-cache) boosting execution performance from external memories.
Security
STM32H7B3 MCUs include the following additional security features:
- Crypto/hash hardware acceleration
- On-the-fly decryption on Octo-SPI external serial flash memory
- Secure Firmware Install (SFI) embedded security services to authenticate and protect your software IPs while performing initial programming.
- Secure Boot Secure Firmware Update (SBSFU)
Power Efficiency
- Dual-power domain architecture enables each power domain to be set in low-power mode to optimize power efficiency
- Embedded SMPS to scale down the supply voltage. It can also be used to supply external circuitry and can also be combined with the LDO for specific use cases
- 120 µA/MHz typical @ VDD = 3.3 V and 25 °C in Run mode (peripherals off) and SMPS
- 32 µA typical in STOP mode (low-power mode)
- 2.2 µA typical in Standby mode (low-power mode)
- 0.74 µA typical in VBAT mode with RTC (low-power mode)
Graphics
- LCD-TFT controller interface with dual-layer support
- Chrom‑ART Accelerator™ boosts graphical content creation while saving core processing power, thus freeing up the MCU for other application needs
- Chrom-GRC™ optimizes RAM use
- JPEG hardware accelerator for fast JPEG encoding and decoding, off-loading the CPU
Read more: STMICROELECTRONICS STM32H7A3/7B3 LINES OF MICROCONTROLLERS INCLUDE AN ARM® CORTEX®-M7 CORE
- What core does the STM32H7A3/7B3 use?
It uses an Arm Cortex-M7 core with a double-precision floating point unit running up to 280 MHz. - How much Flash and SRAM do these MCUs provide?
They provide 1 to 2 Mbytes of Flash and 1.414 Mbytes of SRAM (including TCM and backup SRAM). - What is the TCM SRAM architecture in these MCUs?
TCM includes 192 Kbytes total: 64 Kbytes of ITCM and 128 Kbytes of DTCM for time-critical code and data. - What performance features boost execution from external memory?
L1 cache (16 KB I-cache and 16 KB D-cache) enables 0-wait states and boosts execution from external memory. - What security features are included in STM32H7B3 MCUs?
They include crypto/hash hardware acceleration, on-the-fly decryption for Octo-SPI external flash, Secure Firmware Install services, and Secure Boot Secure Firmware Update. - How do these MCUs optimize power efficiency?
They use a dual-power domain architecture, an embedded SMPS, and multiple low-power modes with specified typical currents. - What are the typical current consumptions in low-power modes?
Typical currents are 120 µA/MHz in Run mode (peripherals off) with SMPS, 32 µA in STOP mode, 2.2 µA in Standby, and 0.74 µA in VBAT mode with RTC. - What graphics accelerators are available?
They include an LCD-TFT controller with dual-layer support, Chrom-ART Accelerator, Chrom-GRC, and a JPEG hardware accelerator. - What package options are available?
They are available in BGA and LQFP packages ranging from 64 to 225 pins.
