Summary of SOM BASED ON MICROCHIP’S LOW-POWER POLARFIRE RISC-V SOC FPGA
The M100PFS is a System-on-Module (SOM) leveraging Microchip's PolarFire SoC FPGA. It integrates six 64-bit RISC-V cores with hardened real-time capabilities and Linux support, offering low power consumption and defense-grade security. The architecture features a secure 5-stage in-order pipeline immune to Meltdown and Spectre exploits, combining deterministic real-time systems with Linux on a single multi-core cluster.
Parts used in the M100PFS:
- Microsemi PolarFire SoC FPGAMPFS025T23KLE
- MPFS095T
- MPFS160T
- MPFS250T254KLE
- Quad 64-bit RV64GC cores
- 64-bit RV64IMAC monitor core
- LPDDR4 RAM
- NOR Flash
- eMMC memory
- Samtec QSH-090-01-F-D-A board-to-board interconnect
The M100PFS is based on the PolarFire SoC FPGA architecture by Microchip and combines high-performance 64-bit RISC-V cores with outstanding FPGA technology. The platform integrates a hardened real-time, Linux capable, RISC-V-based MPU subsystem on the mid-range PolarFire FPGA family, bringing low power consumption, thermal efficiency and defence grade security to embedded systems.
The RISC-V CPU micro-architecture implementation is a simple 5 stage, single issue, in-order pipeline that doesn’t suffer from the Meltdown and Spectre exploits found in common out-of-order machines. All five CPU cores are coherent with the memory subsystem allowing a versatile mix of deterministic real time systems and Linux in a single multi-core CPU cluster.
Features:
- Microsemi PolarFire SoC FPGA
- MPFS025T
23KLE, 68 math blocks, 4x SERDES 12.5Gbit/s, 2x PCIe root port/end point - MPFS095T, available on request
93KLE, 292 math blocks, 4x SERDES 12.5Gbit/s, 2x PCIe root port/end point - MPFS160T, available on request
161KLE, 498 math blocks, 8x SERDES 12.5Gbit/s, 2x PCIe root port/end point - MPFS250T
254KLE, 784 math blocks, 16x SERDES 12.5Gbit/s, 2x PCIe root port/end point
- MPFS025T
- Quad 64-bit RV64GC cores, 667 MHz
- 64-bit RV64IMAC monitor core, 667 MHz
- Processor I/O
- 2x Gigabit Ethernet
- 1x USB 2.0 OTG
- 1x MMC 5.1 SD/SDIO
- 2x CAN 2.0 A and B
- Execute in place Quad SPI flash controller
- 5x multi-mode UARTs
- 2x SPI, 2 I2C
- RTC, GPIO
- 5x watchdog timers
- timers
- Processor to FPGA Interconnect
- 2 64-bit AXI4 processor-to-fabric interfaces
- 3 64-bit AXI4 fabric-to-processor interfaces
- 1 32-bit APB processor-to-fabric interface
- 1/2/4 GByte LPDDR4 RAM dedicated to the HMS
- 1/2/4 GByte LPDDR4 RAM dedicated to the FPGA
- 32 Mbit NOR Flash
- 4 – 64 GByte eMMC memory
- Clock distribution
- default configuration:
- Gigabit Ethernet
- UART
- CAN
- SPI
- I²C
- USB
- single 3,3V supply
- size 74mmx42mm
- 2 x Samtec QSH-090-01-F-D-A board-to-board interconnect
Read more: SOM BASED ON MICROCHIP’S LOW-POWER POLARFIRE RISC-V SOC FPGA
- What architecture does the M100PFS use?
The platform is based on the PolarFire SoC FPGA architecture by Microchip. - How many CPU cores are included in the processor?
The system features Quad 64-bit RV64GC cores running at 667 MHz. - Does the RISC-V implementation suffer from Meltdown or Spectre exploits?
No, the simple 5 stage, single issue, in-order pipeline does not suffer from these exploits. - Can the system run both real-time systems and Linux simultaneously?
Yes, all five CPU cores are coherent with the memory subsystem allowing a mix of both. - What types of memory interfaces are supported for the FPGA?
It supports 1/2/4 GByte LPDDR4 RAM dedicated to the FPGA. - What communication protocols are available on the Processor I/O?
It includes 2x Gigabit Ethernet, 1x USB 2.0 OTG, 1x MMC 5.1 SD/SDIO, 2x CAN 2.0, 5x UARTs, 2x SPI, and 2 I2C. - What is the clock speed of the monitor core?
The 64-bit RV64IMAC monitor core operates at 667 MHz. - What supply voltage does the module require?
The default configuration uses a single 3,3V supply.
