Public Release of ESP32 SoC The Big Brother Of ESP8266




It has been about one year since the announcement of ESP32 SoC and the beginning of its beta testing for some developers.

Public Release of ESP32 SoC The Big Brother Of ESP8266




Last Month we covered the release of ESP-WROOM-32 module datasheet,  which promised that “New SDK features, tutorials and example applications will be released over the next few months.”.

The ESP-32 datasheet was released at the end of August. So let us discover the details of ESP-32 SoC.

ESP32 Connectivity

ESP32 is a single 2.4 GHz Wi-Fi and Bluetooth combo chip available in QFN48 (6×6 mm) package. The new chip supports 802.11 b/g/n/e/i protocols with a data-rate up to 150Mbps. The previous ESP8266EX SoC supports 802.11 b/g/n only.

The security is enhanced in ESP32 by supporting WPA/WPA2/WPA2-Enterprise/Wi-Fi Protected Setup (WPS), while ESP8266EX supports only WPA and WPA2.

ESP32 features a BT4.2 controller and host stack with Xtensa Dual-Core 32-bit LX6 microprocessors up to 240 MHz. Keep in mind that ESP8266 has single core and lacks a bluetooth transceiver.

ESP32 Peripherals

A lot of peripherals were added and enhanced. Up to 18-channel ADC with 12-bit resolution, two DAC channels with 8-bit resolution, 4 × SPI, 2 × I2S, 3 × UART and 2 × I2C.
ESP32 also features 1 host (SD/eMMC/SDIO), 1 slave (SDIO/SPI), Ethernet MAC interface with dedicated DMA and IEEE 1588 support, CAN 2.0, IR (TX/RX), Motor PWM and LED PWM with up to 16 channels.

Internal Sensors

Hall, 10 × touch and temperature sensors are internally available in ESP32 SoC.

Cryptographic Acceleration Hardware

Cryptographic acceleration hardware is for AES, HASH (SHA-2) library, RSA and ECC with Random Number Generator (RNG).

READ  Internet Datalogging With Arduino and XBee WiFi

Memory

ESP32’s internal Memory units are:

  • 448 KBytes ROM for booting and core functions.
  • 520 KBytes on-chip SRAM for data and instruction.
  • 8 KBytes SRAM in RTC, which is called RTC FAST Memory and can be used for data storage and main CPU during RTC Boot from the deep-sleep mode.
  • 1 Kbit of EFUSE, of which 256 bits are used for the system (MAC address and chip configuration) and the remaining 768 bits are reserved for customer applications.

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