TLC NAND flash gets error correction it needs to takeoff

Interest in triple-level cell (TLC) NAND flash is growing and the high density flash memory technology could have cost benefits over single-level NAND in SSDs, but only if endurance and retention questions marks are addressed.

For US-based NAND flash controller supplier Silicon Motion Technology the answer is increased error detection in the flash controller.

It has employed three levels of error correction in its first SATA 6Gbit/s SSD controller to support 1x/1y/1z nm triple-level cell (TLC) NAND devices.TLC NAND flash gets error correction it needs to takeoffIt is expected that TLC NAND devices will account for a growing number of SSD shipments next year.

An example is a 256Gbyte SSD with Toshiba A19 TLC NAND, offering sequential read rate of 524Mbyte/s and sequential write of 400Mbyte/s.

Micron is expected to ship TLC NAND flash fabbed on a 16nm process before the end of the year, which will hit the window for first SSDs in 2015.

“We are aggressively working on our development of our 16nm TLC roadmap in an effort to drive our overall NAND cost competitiveness,” says Micron president Mark Adams, “we expect to see component samples of our 16nm TLC by the end of calendar year with client-based TLC SSD by spring of 2015.”

Also, Samsung’s 840 Series SSD, which uses 3-bit/cell NAND flash.

The important feature of the Silicon Motion TLC NAND flash controller is an error-correcting code engine which provides three levels of error correction and data protection.

Error-correcting code (ECC) is used in NAND flash to compensate for bits that may spontaneously fail during normal device operation.


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