NAND process geometries have become as problematic as logic process geometries with the advantages of further scaling – especially as 3D NAND approaches – being questioned. NAND process geometry is currently at 20nm and should be 10-20nm in 2017, says IC Insights adding “reported minimum feature sizes and mass production definitions are very imprecise and …
Interest in triple-level cell (TLC) NAND flash is growing and the high density flash memory technology could have cost benefits over single-level NAND in SSDs, but only if endurance and retention questions marks are addressed. For US-based NAND flash controller supplier Silicon Motion Technology the answer is increased error detection in the flash controller. It has employed three levels of …
TLC NAND flash gets error correction it needs to takeoff Read More »
