Whether you are designing an SoC, MCU or other chip, the one common heartache is “freezing RTL.” Up until that point, it’s no problem making a change or update, but once it’s frozen, the chip design is “locked in.” A change after that point could require a new spin that is not only costly, but can also significantly delay the chip development schedule.
Now imagine what it would be like to have no deadline to freeze RTL. What chip designer would not want that? The good news is this is now possible using embedded FPGA (eFPGA). With eFPGA, designers have the flexibility to make changes at any point in the chip development process, even in the customers’ systems. While this is beneficial to any chip design team, it is especially beneficial for applications such as data centers, networking, deep learning, artificial intelligence, aerospace and defense.
What is eFPA?
Many people think that eFPGA is the same as traditional FPGA such as those offered by Xilinx and Altera. This is not the case at all. While the technology is similar, eFPGA requires no SERDES and PHYs because on-chip signaling is very fast. Density is also very similar, although some eFPGA platforms are much better than others so designers need to do their homework and shop around for the best platform. The real difference is the users. FPGA chips are used primarily by systems companies, with some in high volume. eFPGAs are used primarily by chip companies who need to integrate a small amount of FPGA-like flexibility into their chips.
An FPGA combines an array of programmable/reconfigurable logic blocks in a programmable interconnect fabric. In an FPGA chip, the outer rim of the chip consists of a combination of GPIO, SERDES and specialized PHYs such as DDR3/4. In advanced FPGAs, the I/O ring is roughly 1/4 of the chip and the “fabric” is roughly 3/4 of the chip. The “fabric” itself is mostly interconnect in today’s FPGA chips where 20-25% of the fabric area is programmable logic and 75-80% is programmable interconnect.
Read more: Taking Advantage of Embedded FPGA (eFPGA)