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SIPEED TEASES TANG NANO SUB-$5 FPGA DEVELOPMENT BOARD WITH ON-BOARD PROGRAMMER

Summary of SIPEED TEASES TANG NANO SUB-$5 FPGA DEVELOPMENT BOARD WITH ON-BOARD PROGRAMMER


The Tang Nano is an ultra-low-cost FPGA development board by Sipeed, priced under $5, designed to make FPGA technology accessible. It features a Gowin Semiconductor GW1N-1 LittleBee FPGA on a 55nm process node, offering 1,152 LUT4s, 72Kb SRAM, and 64Mb PSRAM. The board includes an RGB LED, a 40-pin LCD interface, and a USB Type-C programmer, evolving from an initial $3 concept to meet community feedback with added components.

Parts used in the Tang Nano:

  • Gowin Semiconductor 48-pin FPGA (GW1N-1 LittleBee family)
  • 1,152 four-input lookup tables (LUT4s)
  • 72Kb static RAM (SRAM)
  • 64Mb pseudo-static RAM (PSRAM)
  • On-board RGB LED
  • 40-pin RGB LCD display interface
  • On-board programmer with USB Type-C connectivity
  • Full-colour liquid-crystal display panel (demonstration unit)

FPGA Boards have grown to become one of the “favorites” of the Embedded community. They feature in all kind of applications ranging from automation to DIY Applications, however, typical FPGA boards still cost way more than some other popular boards like the Arduino Microcontroller boards (even though performance is incomparable!). This keeps FPGA boards out of the reach of a good section of the community and to solve this, Sipeed, an open source hardware and embedded computing specialist, recently announced the final specifications for their ultra-low-cost FPGA development board called; the Tang Nano, which according to the firm is expected to cost less than $5.

The Tang Nanos were originally planned by Sipeed to cost only $3 as revealed in an earlier tweet on the company’s Official Twitter handle, but were later estimated at “less than $5 ” by the company in another tweet. While no official specifications was released during the first announcement as only a picture of the board connected with a full-colour liquid-crystal display panel using an on-board display output was included, the announcement generated quite the buzz and led to a lot of people pitching in several ideas and recommendation. Adding support for the suggestions received will no doubt have caused the need for additional components, etc., and most likely be the reason behind the increase in cost.

In the  Twitter update, after revealing the slight increase in cost, the company revealed pictures of the first mass-produced models along with final specifications which include; 1,152 four-input lookup tables (LUT4s), 72Kb static RAM (SRAM), 64Mb pseudo-static RAM (PSRAM), an on-board RGB LED, 40-pin RGB LCD display interface, and on-board programmer with USB Type-C connectivity and that the board will be based on a Gowin Semiconductor 48-pin FPGA.

While a comprehensive official specification needs to be provided by the company’s before it can be verified, a mention on the tweet update that the board uses  the “cheapest’ Gowin Semiconductor 48-pin FPGA could only mean that the board will be based on an FPGA from the GW1N-1 LittleBee family and this means we chould be expecting a 55nm low-power process node.

Read more: SIPEED TEASES TANG NANO SUB-$5 FPGA DEVELOPMENT BOARD WITH ON-BOARD PROGRAMMER

Quick Solutions to Questions related to Tang Nano:

  • What is the expected cost of the Tang Nano?
    The board is expected to cost less than $5.
  • Which FPGA chip powers the Tang Nano?
    The board is based on a Gowin Semiconductor 48-pin FPGA, likely from the GW1N-1 LittleBee family.
  • How much memory does the Tang Nano include?
    It includes 72Kb static RAM and 64Mb pseudo-static RAM.
  • Does the Tang Nano have an onboard programmer?
    Yes, it features an on-board programmer with USB Type-C connectivity.
  • What display interface is supported by the board?
    The board has a 40-pin RGB LCD display interface.
  • Why did the price increase from the initial plan?
    The cost rose due to adding support for suggestions received from the community and additional components.
  • What is the manufacturing process node of the FPGA?
    The FPGA uses a 55nm low-power process node.
  • Who announced the final specifications for the Tang Nano?
    Sipeed, an open source hardware and embedded computing specialist, announced the specifications.

About The Author

Ibrar Ayyub

I am an experienced technical writer holding a Master's degree in computer science from BZU Multan, Pakistan University. With a background spanning various industries, particularly in home automation and engineering, I have honed my skills in crafting clear and concise content. Proficient in leveraging infographics and diagrams, I strive to simplify complex concepts for readers. My strength lies in thorough research and presenting information in a structured and logical format.

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