PULPino – An open-source microcontroller system based on RISC-V
Finally, PULP, goes multicore! We are happy to launch our flagship RISC-V-based parallel-ultra low power open source system. Simply put, OPENPULP, today’s new kid in town, is the most advanced open-source release we have done so far, and a quantum leap ahead in terms of performance, efficiency and completeness.
OPENPULP is an MCU on steroids: an ultra-low power “host” core coupled with a powerful compute engine based on a tightly-coupled cluster of eight cores. To spice things up, we also added an extensive set of IO peripherals and an ultra-efficient IO-DMA which can move data from peripherals to on-chip memory while the cores sleep, and trigger them in action when a data frame is ready. This heterogeneous architecture enables flexible and energy-efficient processing of data streams coming from multiple high-bandwidth sensors such as imagers, microphone arrays, and multi-electrode ExG biosignal arrays.
The brand new 8-core cluster is a true parallel-processing engine, featuring:
- A new low-latency memory interconnect enabling energy-efficient data sharing and atomic accesses on a multi-banked scratchpad memory
- An advanced DMA-engine, capable of 2D data transfers for multi-dimensional double-buffering
- A new event unit for hardware-optimized synchronization and implementation of primitives typical of parallel programming models such as OpenMP.
- A new energy-efficient shared instruction cache optimized for a tightly coupled cluster of processors.
- Support for shared-memory hardware accelerators. We provide examples of on how to add your own Hardware Processing Engines (HWPEs) into the cluster.
… and there is even more to come… Stay tuned!!!
Your PULP team
3.. 2.. 1.. Lift-off: Presenting Ariane
This year ETH Zurich and University of Bologna are celebrating 5 years of collaboration on the PULP project, and we are proud to present the newest member of the PULP family. Ariane is a Linux-ready, application-class, 64-bit RISC-V core supporting (RV64-IMC) written completely in System Verilog, and is available to download from our GitHub page immediately.
Ariane is a 6-stage, single issue, in-order CPU which fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like (Linux, BSD, etc.) operating system. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer, branch history table and a return address stack). The primary design goal was on reducing critical path length to about 20 gate delays.
Following the feedback we will get from our users, we will continue the development of Ariane on the public repositories, and we have many features that we are working on for this core such as:
- IPC improvements
- Double precision floating point unit
- Full support for Atomics
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