Summary of NXP’s MMA8451QR1 Accelerometer
This article discusses the transition from basic MEMS accelerometers to professional-grade solutions for process computer designs, highlighting reliability issues with 3.3V-limited parts and voltage regulator failures in imported breakout boards. It details the NXP MMA8451QR1 accelerometer's features, including I2C interrupts, configurable G-levels, adjustable resolution, and a FIFO buffer to minimize processor load.
Parts used in the NXP MMA8451QR1 Accelerometer Project:
- MEMS-based accelerometer chip
- Micromechanical motion sensor
- Small mass
- Transducer circuits
- I2C interface components
- Decoupling capacitors
- LDO voltage regulators (mentioned as failure points)
Process computer designs usually start out with an accelerometer. As reliability problems creep in, making the switch to a more “professional” solution is beneficial.
Accelerometers are based on the MEMS principle: instead of being a purely solid-state affair, the inside of the chip contains a micromechanical motion sensor along with a small mass. In addition to that, a set of transducer circuits are provided, leading to the block diagram shown in figure one.
Accelerometers can be pretty complex
Adding the part to an application circuit, also, is not difficult. Figure two shows the I2C interface along with a few decoupling capacitors – if all of this is in place, the circuit is ready to rumble.
Tug along a few capacitors, and be happy with your accelerometer…
Sadly, the MMA8451QR1 is yet another 3V6-limited part, and can not live in a 5V domain. This is problematic, as the LDO voltage regulators tended to be responsible for most of the component failures yours truly saw when importing breakout boards from China.
Advanced features
NXP is among the most experienced designers of accelerometer circuits. The I2C interface lets you define all kinds of interrupts, which get fired off even if the main CPU is not monitoring the data stream transmitted via the I2C. Of course, four different G levels can be programmed into the chip, thereby letting you choose between higher accuracy and a larger measurement range.
Processor load is minimised via two nifty design features. First of all, the 14bit resolution can be artificially reduced to 8 bits per channel, thereby cutting bus congestion in half. If that is not enough, a 32 value FIFO buffer allows your CPU to reuse the bus temporarily.
Read more: NXP’s MMA8451QR1 Accelerometer
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Why is switching to a professional solution beneficial?
Switching is beneficial because reliability problems often creep in when using basic designs like standard accelerometers. -
What principle are accelerometers based on?
Accelerometers are based on the MEMS principle, containing a micromechanical motion sensor and a small mass inside the chip. -
What is a limitation of the MMA8451QR1 part?
The MMA8451QR1 is limited to 3V6 and cannot operate in a 5V domain. -
What caused most component failures in imported breakout boards?
LDO voltage regulators were responsible for most of the component failures observed when importing breakout boards from China. -
How does the I2C interface help reduce processor load?
The I2C interface allows defining interrupts that fire even if the main CPU is not monitoring the data stream. -
Can the measurement range be adjusted?
Yes, four different G levels can be programmed into the chip to choose between higher accuracy or a larger measurement range. -
How can bus congestion be reduced?
Bus congestion can be cut in half by artificially reducing the 14bit resolution to 8 bits per channel. -
What feature allows the CPU to reuse the bus temporarily?
A 32 value FIFO buffer allows the CPU to reuse the bus temporarily.
