transistor

CISSOID TO EXHIBIT NEW HIGH TEMPERATURE GATE DRIVERS SIC MOSFETS AND POWER MODULES

CISSOID TO EXHIBIT NEW HIGH TEMPERATURE GATE DRIVERS, SIC MOSFET’S AND POWER MODULES

Electronics News Updates /

CISSOID, the leader in high temperature semiconductors for the most demanding markets, will present new High Temperature Gate Drivers, SiC MOSFET’s and IGBT Power Modules at PCIM 2019, the world’s leading exhibition and conference for power electronics, intelligent motion, renewable energy, and energy management. The company is introducing a new Gate Driver board optimized for 62mm Silicon Carbide (SiC)

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Two bits per transistor high density ROM in Intels 8087 floating point chip

Two bits per transistor: high-density ROM in Intel’s 8087 floating point chip

Electronics News Updates /

The 8087 chip provided fast floating point arithmetic for the original IBM PC and became part of the x86 architecture used today. One unusual feature of the 8087 is it contained a multi-level ROM (Read-Only Memory) that stored two bits per transistor, twice as dense as a normal ROM. Instead of storing binary data, each

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SINGLE ATOM TRANSISTOR WITH ULTRA LOW POWER CONSUMPTION

SINGLE ATOM TRANSISTOR WITH ULTRA-LOW POWER CONSUMPTION

Electronics News Updates /

Karlsruhe Institute of Technology (KIT) researchers in Germany have developed a single-atom transistor that can reduce the power consumption of electronic systems significantly. The device is being developed by Professor Thomas Schimmel and his team at the Institute of Applied Physics (APH). The single-atom transistor switches electrical current by controlled repositioning of a single atom in a gel electrolyte. The

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Imec and Cadence Tape Out Industrys First 3nm Processor Chip

Imec and Cadence Tape Out Industry’s First 3nm Processor Chip

Electronics News Updates /

Nanoelectronics research institute IMEC and Cadence Design Systems have worked together to produce a tape-out for the industry’s first 64bit processor core as a test chip to be built in a nominal 3nm node. The tape-out project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules

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