Summary of Imec and Cadence Tape Out Industry’s First 3nm Processor Chip
IMEC and Cadence successfully tape-out the industry's first 64-bit processor core designed for a nominal 3nm node. This project validates extreme ultraviolet (EUV) and 193 immersion lithography design rules using modified Cadence tool flows, including Innovus and Genus. The design employs a custom 3nm standard cell library with specific metal stack pitches to achieve power, performance, and area targets while exploring advanced transistor structures like nanowires.
Parts used in the 3nm Processor Core:
- Cadence Design Systems tools
- Innovus implementation system
- Genus synthesis tool
- Extreme ultraviolet (EUV) lithography
- 193 immersion (193i) lithography
- 21-nm routing pitch metal stack
- 42-nm contacted poly pitch
- Custom 3nm standard cell library
- Cobalt metals
- Nanowire or nanosheet transistors
Nanoelectronics research institute IMEC and Cadence Design Systems have worked together to produce a tape-out for the industry’s first 64bit processor core as a test chip to be built in a nominal 3nm node. The tape-out project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and Cadence tools.
Cadence and Imec have created and validated GDS files using a modified Cadence tool flow. It is based on a metal stack using a 21-nm routing pitch and a 42-nm contacted poly pitch created with data from a metal layer made in an earlier experiment. The Cadence tools used include the Innovus implementation system that makes use of massively parallel computation for the physical implementation system to achieve power, performance, and area (PPA) targets. The Genus synthesis tool provides RTL synthesis that addresses FinFET process node requirements.
IMEC utilized a standard industry’s 64-bit CPU for the design with a custom 3nm standard cell library. For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.
Imec is starting work on the masks and lithography, initially aiming to use double-patterning EUV and self-aligned quadruple patterning (SAQP) immersion processes. Over time, Imec hopes to optimize the process to use a single pass in the EUV scanner. Ultimately, fabs may migrate to a planned high-numerical-aperture version of today’s EUV systems to make 3-nm chips.
Besides the finer features, the first two layers of 3-nm chips may use different metalization techniques and metals such as cobalt, said Ryoung-Han Kim, an R&D group manager at Imec. The node is also expected to use new transistor designs such as nanowires or nanosheets rather than the FinFETs utilized in today’s 16-nm and finer processes.
Read more: Imec and Cadence Tape Out Industry’s First 3nm Processor Chip
- What is the significance of the IMEC and Cadence collaboration?
The collaboration produced the industry's first 64-bit processor core tape-out for a nominal 3nm node. - How were the GDS files created and validated?
GDS files were created and validated using a modified Cadence tool flow based on specific metal stack pitches. - Which Cadence tools were utilized for physical implementation and synthesis?
The Innovus implementation system was used for physical implementation, and the Genus synthesis tool handled RTL synthesis. - Can double-patterning EUV be used in this project?
Yes, Imec aims to initially use double-patterning EUV alongside self-aligned quadruple patterning immersion processes. - What future migration path do fabs have for 3nm chips?
Fabs may migrate to a planned high-numerical-aperture version of today's EUV systems to make 3-nm chips. - Does the 3nm node use different metalization techniques than previous nodes?
Yes, the first two layers may use different metalization techniques and metals such as cobalt. - What transistor designs are expected for the 3nm node?
The node is expected to use new transistor designs such as nanowires or nanosheets rather than FinFETs. - How does the Innovus system help achieve PPA targets?
Innovus uses massively parallel computation for the physical implementation system to achieve power, performance, and area targets.
