Since the launch of the ESP-01, the ESP series of WiFi modules and WiFi-enabled microcontrollers have endeared themselves to the heart of both hobbyist and electronics design professionals. They have been used for all sorts of projects and while users are still praising the impressive features built into its most recent version, the ESP-32, Espressif systems have announced details of the next one which is the ESP32-s2.
The ESP32-S2 incorporates a Wi-Fi subsystem that integrates a Wi-Fi MAC, Wi-Fi radio and baseband, RF switch, RF balun, power amplifier, low noise amplifier (LNA) among others, with an Xtensa single-core 32-bit LX7 microprocessor clocked at 240 MHz making it useful for WiFi-based solutions without the need for an additional microcontroller. It is an highly-integrated, Low-power, 2.4 GHz WiFi system-on-chip solution. It is an ideal choice for a wide variety of application scenarios relating to wearable electronics, smart home and Internet of Things (IoT) and the ESP32-S2 unlike other ESP processors launched so far, is the first of its kind to come with an in-built USB (OTG) interface, advanced peripheral interfaces, WiFi Time-of-Flight, and hardware security features.
The on-chip memory aboard the ESP32-S2 includes 128 KB ROM, 320 KB SRAM, 16 KB SRAM in RTC and SPI/QSPI/OSPI that supports multiple flash/SRAM chips. It also has various dedicated security features like the Cryptographic hardware accelerators (integrated for RSA and AES algorithms), the Random Number Generator (RNG), flash encryption, secure boot, HMAC, digital signature as well as 4096-bit OTP up to 1792 bits for users.
Some Advanced Peripheral Interfaces Of This Device Include:
- 43 × programmable GPIOs
- 2 × 12-bit SAR ADCs, up to 20 channels
- 2 × 8-bit DAC
- 14 × touch sensing IOs
- 4 × SPI
- 1 × I2S
- 2 × I2C
- 2 × UART
- RMT (TX/RX)
- LED PWM, up to 8 channels
- 1 × full-speed USB OTG
- 1 × temperature sensor
- 1 × DVP 8/16 camera interface, implemented using the hardware resources of I2S
- 1 × LCD interface (8-bit parallel RGB/8080/6800), implemented using the hardware resources of SPI2
- 1 × LCD interface (8/16/24-bit-parallel), implemented using the hardware resources of I2S
There is a favorable trade-off between the power consumption, communication range and data rate of the processor as a result it features fine-grained clock gating, adjustable power amplifier output, and the dynamic frequency and voltage scaling.
Like it’s predecessors there is also a development board based on the ESP32-S2 processor and it has 21-pin I/O headers for expansion, power signal, and rest pins. There also seems to be an SPI flash on the board along with an SPI RAM.