Frequency and Phase Locked Loops (PLL)
The purpose of a PLL is to generate a frequency and phase-locked output oscillation signal.
To achieve this goal, prior art essentially functioned by frequently changing the PLL output frequency according to the phase error (i.e. the faster/slower phase relationship) to generate a momentary, but not static, frequency and phase locked output oscillation signal. This frequent back-and-forth change in VCO frequency creates significant Jitter and a longer settling time because when phase is correct (locked), frequency is likely wrong (unlocked), or when frequency is correct (locked), phase is likely wrong (unlocked).
1. Field of the Invention
The present invention relates to Phase Locked Loops (PLL) including PLL using Voltage Controlled Oscillators (VCO) and Digital Controlled Oscillators (DCO).
2. Description of Prior Art
Analog PLL are generally built with a phase detector, a low pass filter, a VCO and a frequency divider in a negative feedback configuration.
Digital PLL are generally built with a time-to-digital converter, a digital loop filter, a DCO and a frequency divider in a negative feedback configuration.
A VCO or DCO efficiently provides oscillation waveform with variable frequency. PLL synchronises VCO / DCO frequency to input reference frequency feedback.
VCO output frequency Fvco = Kvco * Vctl, where Kvco is constant gain over most of the usable control voltage range, and Vctl is VCO control voltage.
An important part of a PLL is the phase detector or time-to-digital converter. This compares the phase of the two inputs to the detector and produces a corrective voltage signal to control the oscillator so that the phase between the inputs becomes zero. The two inputs of the phase detector are usually the reference and the divided output of VCO or DCO.
The purpose of PLL is to generate a frequency and phase locked output oscillation signal.
However, prior art cannot achieve the desired purpose because (1) VCO and DCO are frequency variable and controllable, they are not phase variable and controllable and (2), using phase error to correct frequency is improper because it is a conflict control and leads to infinite jitter in PLL output (i.e. deviation of VCO/DCO output edges from their ideal placement in time). Due to these two reasons, neither frequency nor phase will actually be locked – making PLL performance difficult to improve.
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