The ISLA118P50 is a low-power, high-performance, 500MSPS analog-to-digital converter designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process. The ISLA118P50 is part of a pin-compatible portfolio of 8, 10 and 12-bit A/Ds. This device is an upgrade of the KAD551XP-50 product family and is pin similar.
The device utilizes two time-interleaved 250MSPS unit A/Ds to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Intersil Interleave Engine (I2E) performs automatic fine correction of offset, gain, and sample time skew mismatches between the unit A/Ds to optimize performance. No external interleaving algorithm is required.
A serial peripheral interface (SPI) port allows for extensive configurability of the A/D. The SPI also controls the interleave correction circuitry, allowing the system to issue continuous calibration commands as well as configure many dynamic parameters.
Digital output data is presented in selectable LVDS or CMOS formats. The ISLA118P50 is available in a 72-contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C).
- Radar and Electronic/Signal Intelligence
- Broadband Communications
- High-Performance Data Acquisition
- 1.15GHz Analog Input Bandwidth
- 90fs Clock Jitter
- Automatic Fine Interleave Correction Calibration
- Multiple Chip Time Alignment Support via the Synchronous Clock Divider Reset
- Programmable Gain, Offset and Skew control
- Over-Range Indicator
- Clock Phase Selection
- Nap and Sleep Modes
- Two’s Complement, Gray Code or Binary Data Format
- DDR LVDS-Compatible or LVCMOS Outputs
- Programmable Test Patterns and Internal Temperature Sensor
Intersil has introduced 468mW 12bit 500Msample/s ADC.
“It’s five times lower power than any competing 12bit 500Msample/s ADC,” claimed the firm.
Called ISLA112P50, it is built using Intersil’s proprietary technology on a standard CMOS process, and has been developed for broadband communications, radar, lidar, and data acquisition systems.
Inside are a pair of time-interleaved 250Msample/s ADCs, with technology to automatically correct for offset, gain and sample time skew mismatch between the pair.
Analogue input bandwidth is 1.15GHz, SNR is 65.8dBFS, and SFDR is 80dBc for an input frequency of 190MHz.
Digital output data is available in either LVDS or CMOS formats and a synchronous clock divider reset aids in time alignment of multiple devices.
“Specified min/max digital interface timing with respect to the ADC input clock improves system reliability by allowing designers to close timing and select the most cost-efficient FPGA that meets the timing requirements,” said Intersil.
External systems can issue continuous calibration commands and configure dynamic parameters through a serial peripheral interface.
For more read: Intersil’s half Watt 12bit ADC hits 500Msample/s