Summary of Intersil’s half Watt 12bit ADC hits 500Msample/s
The article describes Intersil's ISLA118P50 (and mentions ISLA112P50) low-power, high-performance 12-bit ADCs that achieve 500 MSPS using two time-interleaved 250 MSPS unit ADCs with automatic interleave correction (I2E/FemtoCharge). They offer 1.15 GHz input bandwidth, selectable LVDS or CMOS outputs, SPI configuration including continuous calibration, programmable gain/offset/skew, and operate over -40°C to +85°C in a 72-contact QFN package.
Parts used in the ISLA118P50 / ISLA112P50 Project:
- ISLA118P50 12-bit 500MSPS ADC (pin-compatible family member)
- ISLA112P50 12-bit 500MSPS ADC (related half-watt device referenced)
- Synchronous clock source (500MHz conversion clock)
- Serial Peripheral Interface (SPI) for configuration and calibration
- LVDS or LVCMOS digital output interface
- 72-contact QFN package with exposed paddle (packaging)
- External system or FPGA for data capture and timing alignment
- Clock distribution/reset for synchronous clock divider reset (multi-chip alignment)
Description
The ISLA118P50 is a low-power, high-performance, 500MSPS analog-to-digital converter designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process. The ISLA118P50 is part of a pin-compatible portfolio of 8, 10 and 12-bit A/Ds. This device is an upgrade of the KAD551XP-50 product family and is pin similar.
The device utilizes two time-interleaved 250MSPS unit A/Ds to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Intersil Interleave Engine (I2E) performs automatic fine correction of offset, gain, and sample time skew mismatches between the unit A/Ds to optimize performance. No external interleaving algorithm is required.
A serial peripheral interface (SPI) port allows for extensive configurability of the A/D. The SPI also controls the interleave correction circuitry, allowing the system to issue continuous calibration commands as well as configure many dynamic parameters.
Digital output data is presented in selectable LVDS or CMOS formats. The ISLA118P50 is available in a 72-contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C).
Applications
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- Radar and Electronic/Signal Intelligence
- Broadband Communications
- High-Performance Data Acquisition
Key Features
-
- 1.15GHz Analog Input Bandwidth
- 90fs Clock Jitter
- Automatic Fine Interleave Correction Calibration
- Multiple Chip Time Alignment Support via the Synchronous Clock Divider Reset
- Programmable Gain, Offset and Skew control
- Over-Range Indicator
- Clock Phase Selection
- Nap and Sleep Modes
- Two’s Complement, Gray Code or Binary Data Format
- DDR LVDS-Compatible or LVCMOS Outputs
- Programmable Test Patterns and Internal Temperature Sensor
Intersil has introduced 468mW 12bit 500Msample/s ADC.
“It’s five times lower power than any competing 12bit 500Msample/s ADC,” claimed the firm.
Called ISLA112P50, it is built using Intersil’s proprietary technology on a standard CMOS process, and has been developed for broadband communications, radar, lidar, and data acquisition systems.
Inside are a pair of time-interleaved 250Msample/s ADCs, with technology to automatically correct for offset, gain and sample time skew mismatch between the pair.
Analogue input bandwidth is 1.15GHz, SNR is 65.8dBFS, and SFDR is 80dBc for an input frequency of 190MHz.
Digital output data is available in either LVDS or CMOS formats and a synchronous clock divider reset aids in time alignment of multiple devices.
“Specified min/max digital interface timing with respect to the ADC input clock improves system reliability by allowing designers to close timing and select the most cost-efficient FPGA that meets the timing requirements,” said Intersil.
External systems can issue continuous calibration commands and configure dynamic parameters through a serial peripheral interface.
For more read: Intersil’s half Watt 12bit ADC hits 500Msample/s
- What is the sample rate of the ISLA118P50?
The ISLA118P50 achieves a 500MSPS sample rate using two time-interleaved 250MSPS unit ADCs. - How does the device correct interleave mismatches?
It uses the proprietary Intersil Interleave Engine (I2E) to perform automatic fine correction of offset, gain, and sample time skew mismatches. - Can the ADC outputs be configured as LVDS?
Yes, digital output data is available in DDR LVDS-compatible or LVCMOS formats. - Does the ADC support continuous calibration?
Yes, the SPI allows external systems to issue continuous calibration commands and configure dynamic parameters. - What is the analog input bandwidth?
The analog input bandwidth is 1.15GHz. - What temperature range is performance specified over?
Performance is specified over the industrial range of -40°C to +85°C. - Are there power-saving modes?
Yes, the device includes Nap and Sleep modes. - What data formats does the ADC support?
It supports Two's Complement, Gray Code, or Binary data formats. - What features assist multi-chip time alignment?
The synchronous clock divider reset aids multiple-chip time alignment. - What test and monitoring features are available?
The ADC provides programmable test patterns and an internal temperature sensor.
