Frequency and Phase Locked Loops (PLL)




The purpose of a PLL is to generate a frequency and phase-locked output oscillation signal.

To achieve this goal, prior art essentially functioned by frequently changing the PLL output frequency according to the phase error (i.e. the faster/slower phase relationship) to generate a momentary, but not static, frequency and phase locked output oscillation signal. This frequent back-and-forth change in VCO frequency creates significant Jitter and a longer settling time because when phase is correct (locked), frequency is likely wrong (unlocked), or when frequency is correct (locked), phase is likely wrong (unlocked).

Frequency and Phase Locked Loops

1. Field of the Invention

The present invention relates to Phase Locked Loops (PLL) including PLL using Voltage Controlled Oscillators (VCO) and Digital Controlled Oscillators (DCO).
2. Description of Prior Art




Analog PLL are generally built with a phase detector, a low pass filter, a VCO and a frequency divider in a negative feedback configuration.

For more detail: Frequency and Phase Locked Loops (PLL)




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READ  ICS501 simple frequency multiplier

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