TI intros its lowest noise octal 12-bit ADC

Using CMOS process technology and innovative circuit techniques, the ADS5294 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.

The ADS5294 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.

Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. The ADC resolution can be programmed to 12 bit or 14 bit through registers. A very unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.

Features

• Maximum Sample Rate: 80 MSPS/14-Bit
• High Signal-to-Noise Ratio
  • 75.5-dBFS SNR at 5 MHz/80 MSPS
  • 78.2-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter Enabled
  • 84-dBc SFDR at 5 MHz/80 MSPS
• Low Power Consumption
  • 58mW/CH at 50 MSPS
  • 77 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
• Digital Processing Block
  • Programmable FIR Decimation Filter and Oversampling to Minimize
    Harmonic Interference
  • Programmable IIR High Pass Filter to Minimize DC Offset
  • Programmable Digital Gain: 0 dB to 12 dB
  • 2- or 4-Channel Averaging
• Flexible Serialized LVDS Outputs:
  • One or Two Wires of LVDS Output Lines per Channel Depending on ADC
    Sampling Rate
  • Programmable Mapping Between ADC Input Channels and LVDS Output
    Pins-Eases Board Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver

   

Texas Instruments has introduced a low noise octal-channel, 14-bit analogue-to-digital converter (ADC) and a sampling frequency of up to 80MSPS.

The ADS5294 has specified signal-to-noise ratio (SNR) of 75.5dBFS at 5MHz.

Power consumption is 77mW per channel at 80MSPS.

On-chip TI has included a digital processing block, a low-frequency noise suppression mode and programmable input-to-output mapping.

Using the ADS5294, digital data can be output over one or two wires of LVDS pins per channel reducing the number of interface lines. This creates a two-wire interface which keeps the serial data rate low allowing designers to use low cost FPGAs.

The ADS5294 is available in a 12mm x 12mm, 80-pin QFP package.

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