# Simple circuit lets you characterize JFETs

When working with discrete JFETs, designers may need to accommodate a large variation in device parameters for a given transistor type. A square-law **equation** is usually used as an approximate model for the drain-current characteristic of the JFET: I_{D}=β(V_{GS}−V_{P})^{2}, where I_{D} is the drain current, V_{GS} is the gate-to-source voltage, β is the transconductance parameter, and V_{P} is the gate pinch-off voltage. With this approximation, the following **equation** yields the zero-bias drain current at a gate-to-source voltage of 0V: I_{DSS}=βV_{P} ^{2}, where I_{DSS} is the zero-bias drain current.

Although you can design around a certain amount of device variation for a mass-produced circuit, you sometimes need a tool to quickly characterize an assortment of discrete devices. This tool allows you to select a device that will optimize one circuit or perhaps to find a pair of devices with parameters that match reasonably well.

**Figure 2** shows a simple test circuit for this purpose. Although the **figure** shows the JFET as an N-channel device, the JFET DUT (device under test) may be of either polarity, as selected by switch S_{1}. An external voltmeter connects to the terminals on the right. Switch S_{2} selects two distinct measurement modes—one for the pinch-off voltage and another for the zero-bias drain current. In the pinch-off-voltage mode, the external voltmeter directly reads the pinch-off voltage; in the zero-bias-drain-current mode, the measured voltage is the zero-bias drain current across an apparent resistance of 100Ω.

With S_{2} in the pinch-off-voltage mode, R_{1} allows a few microamps of drain current to flow in the JFET under test, and the source voltage is a close approximation of the negative of the pinch-off voltage. The op amp acts as a unity-gain buffer, with negative feedback through R_{3}, so you can directly read the negative of the pinch-off voltage with the external voltmeter.

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